Device heterogeneity is an important dimension to add into future
notions of heterogeneous processing. Steep slope devices, such as
TFETs, allow designers to aim for new points in the design space that
were previously impractical. However, these new devices augment CMOS,
rather than replace it, representing a shift in the balance of optimal
exploitation of ILP, TLP, and DLP in heterogeneous multiprocessor and
SoC designs rather than a revolution. We have shown that, analogous to
architectural and microarchitectural heterogeneity in CMOS processors,
the utility of the additional core-implementation types varies by
application, but offers real overall benefits across entire workloads:
we show exploitation of TLP and ILP yielding 19\% and 47\%
peak improvements in performance for iso-thermal execution, respectively,
and analysis of accelerators synthesized in both CMOS and TFET
libraries indicates that TFETs are well suited to improve DLP-heavy
workloads.

% LocalWords:  TFETs CMOS ILP TLP DLP SoC microarchitectural TFET
